Power devices are widely used to carry large currents and support high voltages. Modern power devices are generally fabricated from monocrystalline silicon semiconductor material. One widely used power device is the power Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In a power MOSFET, a control signal is supplied to a gate electrode that is separated from the semiconductor surface by an intervening insulator, which may be, but is not limited to, silicon dioxide. Current conduction occurs via transport of majority carriers, without the presence of minority carrier injection that is used in bipolar transistor operation. Power MOSFETs can provide an excellent safe operating area, and can be paralleled in a unit cell structure.
As is well known to those having skill in the art, power MOSFETs may include a lateral structure or a vertical structure. In a lateral structure, the drain, gate and source terminals are on the same surface of a substrate. In contrast, in a vertical structure, the source and drain are on opposite surfaces of the substrate.
Recent development efforts in power devices have also included investigation of the use of silicon carbide (SiC) devices for power devices. Silicon carbide has a wide bandgap, a lower dielectric constant, a high breakdown field strength, a high thermal conductivity, and a high saturation electron drift velocity compared to silicon. These characteristics may allow silicon carbide power devices to operate at higher temperatures, higher power levels and with lower specific on-resistance than conventional silicon-based power devices. A theoretical analysis of the superiority of silicon carbide devices over silicon devices is found in a publication by Bhatnagar et al. entitled “Comparison of 6H—SiC, 3C—SiC and Si for Power Devices”, IEEE Transactions on Electron Devices, Vol. 40, 1993, pp. 645–655. A power MOSFET fabricated in silicon carbide is described in U.S. Pat. No. 5,506,421 to Palmour entitled “Power MOSFET in Silicon Carlide” and assigned to the assignee of the present invention.
A number of silicon carbide power MOSFET structures have been described in the literature. See e.g. U.S. Pat. No. 5,506,421; A. K. Agarwal, J. B. Casady, L. B. Rowland, W. F. Valek, M. H. White, and C. D. Brandt, “1.1 kV 4H—SiC Power UMOSFET's,” IEEE Electron Device Letters, Vol. 18, No. 12, pp. 586–588, December 1997; A. K. Agarwal, J. B. Casady, L. B. Rowland, W. F. Valek and C. D. Brandt, “1400 V 4H—SiC Power MOSFETs,” Materials Science Forum Vols. 264–268, pp. 989–992, 1998; J. Tan, J. A. Cooper, Jr., and M. R. Melloch, “High-Voltage Accumulation-Layer UMOSFETs in 4H—SiC,” IEEE Electron Device Letters, Vol. 19, No. 12, pp. 487–489, December 1998; J. N. Shenoy, J. A. Cooper and M. R. Melloch, “High-Voltage Double-Implanted Power MOSFET's in 6H—SiC,” IEEE Electron Device Letters, Vol. 18, No. 3, pp. 93–95, March 1997; J. B. Casady, A. K. Agarwal, L. B. Rowland, W. F. Valek, and C. D. Brandt, “900 V DMOS and 1100 V UMOS 4H—SiC Power FETs,” IEEE Device Research Conference, Ft. Collins, Colo., Jun. 23–25, 1997; R. Schomer, P Friedrichs, D. Peters, H. Mitlehner, B. Weis and D. Stephani, “Rugged Power MOSFETs in 6H—SiC with Blocking Capability up to 1800 V,” Materials Science Forum Vols. 338–342, pp. 1295–1298, 2000; V. R. Vathulya and M. H. White, “Characterization of Channel Mobility on Implanted SiC to determine Polytype suitability for the Power DIMOS structure,” Electronic Materials Conference, Santa Barbara, Calif., Jun. 30–Jul. 2, 1999; A. V. Suvorov, L. A. Lipkin, G. M. Johnson, R. Singh and J. W. Palmoutr, “4H—SiC Self-Aligned Implant-Diffused Structure for Power DMOSFETs,” Materials Science Forum Vols. 338–342, pp. 1275–1278, 2000; P. M. Shenoy and B. J. Baliga, “The Planar 6H—SiC ACCUFET: A New High-Voltage Power MOSFET Structure,” IEEE Electron Device Letters, Vol. 18, No. 12, pp. 589–591, December 1997; Ranbir Singh, Sei-Hyung Ryu and John W. Palmour, “High Temperature, High Current, 4H—SiC Accu-DMOSFET,” Materials Science Forum Vols. 338–342, pp. 1271–1274, 2000; Y. Wang, C. Weitzel and M. Bhatnagar, “Accumulation-Mode SiC Power MOSFET Design Issues,” Materials Science Forum Vols. 338–342, pp. 1287–1290, 2000; A. K. Agarwal, N. S. Saks, S. S. Mani, V. S. Hegde and P. A. Sanger, “Investigation of Lateral RESURF, 6H—SiC MOSFETs,” Materials Science Forum Vols. 338–342, pp. 1307–1310, 2000; and Shenoy et al., “High-Voltage Double-Implanted Power MOSFET's in 6H—SiC,” IEEE Electron Device Letters, Vol. 18, No. 3, March 1997, pp. 93–95.
One widely used silicon power MOSFET is the double diffused MOSFET (DMOSFET) that is fabricated using a double-diffusion process. A conventional DMOSFET 510 in silicon is illustrated in FIG. 1A. In these devices, a p-base region 514 and an n+ source region 516 are diffused in a substrate 512 through a common opening in a mask. The p-base region 514 is driven in deeper than the n+ source region 516. The difference in the lateral diffusion between the p-base 514 and n+ source regions 16 forms a surface channel region. A gate oxide 518 is provided on the substrate 512 and a gate contact 520 on the gate oxide 518. A source contact is provided on the substrate 512 between the n+ source regions 516. A drain contact 524 is provided on the substrate 512 opposite the source contact 522. An overview of power MOSFETs including DMOSFETs may be found in the textbook entitled “Power Semiconductor Devices” by B. J. Baliga, published by PWS Publishing Company, 1996, and specifically in Chapter 7, entitled “Power MOSFET”, the disclosure of which is hereby incorporated herein by reference. The DMOSFET structure has also been fabricated in silicon carbide, however, because of the low diffusion of dopants in silicon carbide, other techniques, such as double implants, have been used in fabricating DMOSFETs in silicon carbide. Thus, the term “DMOSFET” is used herein to refer to a structure similar to that of FIG. 1A having a base or well region and source regions in the base or well region irrespective of the methods used in fabricating the structure.
As illustrate in FIG. 1B, the power MOSFET of FIG. 1A can be modeled as a switch and an anti-parallel diode (the built-in body diode). A power MOSFET is a majority carrier device with very high switching speeds. However, in many cases, the switching of the power MOSFET is limited by the speed of the built-in body diode. The anti-parallel p-n diode is built into the MOSFET between the p-base region 514 and the n-type drift region of the substrate 512. In the first quadrant of operation (positive drain current and drain voltage), the device works as a switch. In the third quadrant of operation (negative drain current and drain voltage), with a gate bias of 0 volts, the device works as a PiN diode. However, the built-in body diode may limit operation of the device at high frequencies, for example, frequencies greater than 100 kHz. Such may be the case because the built-in body diode is a relatively slow minority carrier device. A PiN diode has a high minority carrier lifetime and may often fail to keep Up with the switching speed of the MOSFET. Therefore, the switching speed of the power MOSFET may be need to reduced. Alternatively the use of series Schottky diodes with an ultra fast recovery rectifier in an anti-parallel configuration for the whole assembly may be used or a “snubber” circuit have been proposed, for example, in high speed applications such as pulse width modulated DC motor controllers. See e.g. Motorola Power MOSFET Transistor Databook, 4th edition, Motorola, Inc., 1989. However, external snubber circuits may be expensive and bulky.
The use of an external fast recovery anti-parallel diode is described by Mondal et al., “An Integrated 500-V Power DMOSFET/Antiparallel Rectifier Device with Improved Diode Reverse Recovery Characteristics,” IEEE Electron Device Letters, Vol. 23, No. 9, September 2002. However, this method may be ineffective because in the reverse recovery mode the slowest diode provides the dominant current path. Thus, the current rating of the external fast recovery diode should be much higher than the built-in body diode of the MOSFET so that most of the on-current flows through the external diode, leaving a very small amount of current flowing through the body diode, resulting in a very small reverse recovery charge in the body diode. However, this leads to large parasitic output capacitance of the MOSFET-diode pair since a large area diode is needed in parallel configuration.
Mondal et al. also describes an attempt to integrate a Merged PiN Schottky (MPS) diode with a silicon power DMOSFET to achieve better reverse recovery characteristics. The DMOSFET with the integrated MPS diode showed a 30% decrease in peak reverse current and minority carrier stored charge.